Re: water cooled

Rohit Khare (
Tue, 25 Feb 1997 12:28:27 -0500 (EST)

Tim found an excellent article. For those of you who haven't yet deciphered
the three line URL, here's the text.


The refrigerator under the table

By Ron Wilson

When is a chip an engineering device, and when is it a public-relations
device? Some of the presentations at the International Solid-State Circuits
Conference begged the question.

The issue came up early in the conference when NEC-which certainly has nothing
to prove in the realm of DRAM-design skill-gave a paper on a 4-Gbit DRAM.
Now, everyone understands that the papers at ISSCC describe engineering
prototypes, and no one expects the masks to go into production. But NEC
launched itself deep into gray area this time.

The chip it described was an enormous array of four-level analog storage
cells, with the necessary bit lines, sense amps and so forth to make a 4-Gbit
DRAM. At least, that's what the PR said.

In fact, the chip was mainly used to test the four-level storage cell and
the sense amp at a conceptual level. Engineers are still a long way from
being able to move charge from the bit cell to the sense amps with any

In other words, there was probably no engineering purpose for building an
entire, but almost entirely non-functional "4-Gbit" chip. Its real reason
for being was its public-relations value.

A second example came on the next day of the conference, when Intel Corp.
presented an engineering test vehicle for the soon-to-be-announced Klamath
CPU. Intel said (and the headlines obediently echoed) that it was showing a
Pentium Pro-type CPU running at 300 MHz-a startling achievement.

A little too startling. As it turned out-and Intel was quite frank with the
engineering audience that heard its paper-the remarkable clock rate was
achieved by cooling the chip to nearly 0 degrees C. In the demo suite where
the company entertained the press, it actually had a PC running at 300 MHz-with
a cooling unit hidden beneath the draped table on which the PC rested.

Unfortunately, there was no easy way to cool the L2 caches, so the CPU was
running significantly faster than its external cache.

The confusion didn't end there. Intel's paper described an elegant new cache
interface, called Source-Synchronous, that will permit the CPU chip to
communicate at conventional CMOS levels to its external cache chips at very
high clock rates. But Intel's paper didn't seem to remember that the company
has not put that feature into the CPU, because of the practical need to work
with commodity burst-synchronous SRAMs.

So the bottom line was that Intel showed a CPU working in an unrealistic
environment, with an impractical cache structure. And then it added to the
confusion by describing a solution to the cache problem that it in fact did
not adopt.

Intel did not intend to mislead its engineering audience. But the effect on
the consumer press was predictable puzzlement.

One has to wonder. By any standard, the Klamath CPU is a substantial engineering
achievement. Wouldn't it be sufficient, at an engineering conference, just
to describe what the engineers did? At what point does it become the right
of the marketing department to "tune" the message for the non-technical press?

We would like to suggest that ISSCC return to its original attitude toward
such hype. The chips described at the conference should be demonstrably
functional, in their intended use and intended environment. Let marketing
communicate to the business press through some other channel.

If we don't impose some discipline, it won't be long before all the chips
described at ISSCC will belong to a special session: "Developments in

-Ron Wilson is managing editor, semiconductors, for EE Times.