From: Tom Whore (tomwhore@inetarena.com)
Date: Fri Oct 20 2000 - 13:10:03 PDT
On Fri, 20 Oct 2000 strata@KnowNow.com wrote:
--]And if we layer it with split Hostess TM Twinkies in an attractive serving
--]dish, grease, unmold, and cable up, it becomes a supercomputer that will
--]proudly serve in a variety of social occasions, from a backyard BBQ to
--]a webgrrrl's high tea.
--]
--]OK, Tom, whazzit?
--]
OK since im heading out the office early today ill give the unanswered
answer. And I thought this would be a gimme.
http://www.realworldtech.com/page.cfm?ArticleID=RWT101600000000
The conventional wisdom is that the battle for technical and performance
leadership in the high end 64 bit microprocessor market will be a two way
fight between future IA-64 and Alpha devices. With the recent disclosure
of detailed information about the processor core of the POWER4 server MPU
at Microprocessor Forum 2000, it appears IBM is preparing to leapfrog its
way to preeminence in the 64 bit MPU market within the next 12 months.
Pulling hard on every technological lever at its disposal, IBM has
aggressively, and apparently successfully, pushed the envelope forward in
many processor related engineering disciplines.
IBM has designed perhaps the most capable superscalar RISC core yet seen,
and implemented the design in a state of the art 0.18 um SOI CMOS process
utilizing 7 layers of copper interconnect. Not satisfied with that, IBM
places not one but two processor cores on a huge 400 mm2 die with three
independent, high bandwidth L2 caches, each approximately half a megabyte
in capacity [1]. In addition, the POWER4 device integrates controller
logic for external L3 cache and main memory, along with interprocessor
communications channels for a total chip complexity of about 170 million
transistors. To keep such a powerful and hungry processing complex fed,
this chip includes very wide high speed buses which require about 5200
off-chip solder-ball pads, of which roughly 2200 are I/O signals, while
the remainder provide power and ground connections.
The icing on the POWER4 cake is the packaging technology, which is shown
below in Figure 1.
Drawing heavily on IBMs extensive experience over the last several decades
in designing and manufacturing large and sophisticated multi-chip modules
(MCMs) for its mainframes, four separate POWER4 dice are combined on a
single ceramic MCM mounted in a rugged metal frame less than 5 inches on a
side. This single unit, resembling a S/390 mainframe thermal conduction
module (TCM), contains the core of a tightly coupled 8-way symmetric
multiprocessor (SMP) server system.
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