Re: Handel-C (compile to wire, not code)

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From: Tony Finch (
Date: Sun Oct 08 2000 - 13:45:28 PDT

"Robert S. Thau" <> wrote:
>Eugene Leitl writes:
> > The reason why this is not being done: 1) embedded RAM processes are
> > very new, and SRAM cells take up 4-6 times the space of a DRAM cell,
> > so that makes for very small memory grains. 2) the resulting
> > architecture (100 of CPUs with few ~MBytes memory grains and hardware
> > message passing) would weird out 99% of software developers, and we
> > can't yet import H1Bs from Mars or the galactic halo.
>FWIW, there are several active research projects in academia trying to
>build machines like this, and figure out what to do with them. I
>don't follow the literature enough to track them all, but the
>Amorphous Computing and Raw chip projects at MIT come to mind, as does
>the Berkeley Iram project. (Google will get you pointers to all of
>them, if you're curious).

It sounds to me like a REALLY old idea: the transputer. The difference
of course is that you're thinking in terms of 2000 technology instead
of 1985.

I worked for Inmos for a year before starting university at the time
when they were debugging the T9000. The problems they had with that
chip killed the technology, and by that time people had started using
general-purpose CPUs as the basis for large-scale multiprocessors and
they had replaced the transputer interconnects with their own designs.
(e.g. Meiko, the supercomputer company next door to Inmos.)

There was some really cool technology in the T9, though. The
next-generation transputer links have become the basis for Firewire.
The crossbar switch technology that tied the CPU together was also
used for a cool ATM switch chip. The stuff they did to optimise the
execution of the weird stack-based transputer instruction set was way
ahead of what others were doing. SGS-Thomson, who bought Inmos, still
get a lot of benefit from the Inmos silicon process patents.


en oeccget g mtcaa    f.a.n.finch
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eatp o v eiti i d.

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