1999 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE

Tim Byars (tbyars@earthlink.net)
Fri, 29 Jan 1999 08:32:05 -0800


5.4
A 7th-Generation x86 Microprocessor
3:15 PM

V. Andrade, R. Burd, G. Constant, J. Correll, M. Crowley, M. Golden, S.
Hesley, N. Hopkins, S. Johnson, R. Khondker, D. Meyer,
J. Moench, H. Partovi, R. Posey, F. Weber, J. Yong
Advanced Micro Devices, Austin, TX
A 7th generation x86 microprocessor fetches,decodes, and retires three x86
instructions per cycle in a 15-stage pipeline. The chip uses 0.25=B5m
six-layer metal CMOS plus tungsten local interconnect.

5.5
An Out-of-Order Three-Way Superscalar Multimedia h5 Floating-Point Unit
3:45 PM

M. Golden, N. Juffa, S. Meier, S. Oberman, H. Partovi, A. Scherer,
=46. Weber
Advanced Micro Devices, Sunnyvale, CA
An x87-compatible out-of-order superscalar floating-point unit in 0.25=B5m
six-layer-metal CMOS executes traditional floating-point instructions
at two FLOPS per cycle peak rate, 3DNow! SIMD instructions at four FLOPS
per cycle peak rate, and up to three MMX SIMD instructions
per cycle.

5.6
A 450MHz PowerPC TM Microprocessor with Enhanced Instruction Set and
Copper Interconnect
4:15 PM

J. Alvarez, E. Barkin, C.-C. Chao, B. Johnson, M. D'Addeo,
=46. Lassandro, C. Nicoletta, P. Patel, P. Reed, D. Reid, H. Sanchez,
J. Siegel, M. Snyder, S. Sullivan, S. Taylor, M. Vo
Motorola Somerset Design Center, Austin, TX
A 450MHz 7W microprocessor with an AltiVecTM instruction set implementation
and high memory bandwidth is fabricated in 1.8V CMOS
with copper interconnect. A crossbar circuit that implements the permute
instruction and a programmable 3.3/2.5/1.8V I/O buffer are used. The
10.5M-transistor chip on a 83=B5m2 die has estimated SPECint95 and SPECfp95
performance of 20.

5.7
A 600MHz IA-32 Microprocessor with Enhanced Data Streaming for Graphics
and Video
4:45 PM

R. Senthinathan, S. Fischer, H. Rangchi, H. Yazdanmehr
Intel Corp., Folsom, CA
A next-generation P6 microprocessor adds 67 instructions for data
streaming. Circuit enhancements include multi-grid C4 power distribution,
decoupling techniques, improvements in dynamic circuits, and process
voltage and temperature-compensated I/O buffer designs. The
processor in 0.25=B5m 5-layer-metal CMOS achieves 600MHz.

CONCLUSION
5:15 PM

--

If you must choose between two evils, pick the one you've never tried before. ...Steven Wright

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